20171025 計結

EDA playground
https://www.edaplayground.com/

t_Full_Adder.v (testbench)放左邊
Full_Adder.v (module)放右邊
檔案用貼上別upload

Tools & Simulators
選Icarus Verilog

Full_Adder FA_1(.a(a), .b(b), .ci(ci), .sum(sum), .cout(cout));
input reg 
output wire

$dumpfile("Full_Adder.vcd");
$dumpvars;
輸出file可以看waveform

initial #1000 $stop;
經過一千個單位時間會停下來

verilog-ex
// Code your design here
timescale 1 ns/ 1 ns

module alu (src_a, src_b, c, data_out);

input [7:0] src_a, src_b;
input [2:0] c;
output [7:0] data_out;

/* implement here */
reg [32:0] temp;
assign data_out = temp[32];

initial begin
if(c == 1) begin
  temp = src_a + src_b;
end
else if(c == 2) begin
  temp = src_a - src_b;
end
else if(c == 3) begin
  temp = src_a & src_b;
end
else if(c == 4) begin
  temp = src_a | src_b;
end
else if(c == 5) begin
  temp = src_a ^ src_b;
end

end


endmodule